ROOT logo
#ifndef __TMrbCaen_V879_h__
#define __TMrbCaen_V879_h__

//_________________________________________________[C++ CLASS DEFINITION FILE]
//////////////////////////////////////////////////////////////////////////////
// Name:           expconf/inc/TMrbCaen_V879.h
// Purpose:        Define experimental configuration for MARaBOU
// Class:          TMrbCaen_V879        -- 32 chn peak sensing ADC
// Description:    Class definitions to implement a configuration front-end for MARaBOU
// Author:         R. Lutter
// Revision:       $Id: TMrbCaen_V879.h,v 1.3 2008-01-14 09:48:51 Rudolf.Lutter Exp $       
// Date:           
// Keywords:
//////////////////////////////////////////////////////////////////////////////

namespace std {} using namespace std;

#include <cstdlib>
#include <iostream>
#include <sstream>
#include <iomanip>
#include <fstream>

#include "Rtypes.h"
#include "TSystem.h"
#include "TObject.h"

#include "TMrbVMEModule.h"

class TMrbVMEChannel;
class TMrbSubevent;

//______________________________________________________[C++ CLASS DEFINITION]
//////////////////////////////////////////////////////////////////////////////
// Name:           TMrbCaen_V879
// Purpose:        Define a VME adc/tac type CAEN V879
// Description:    Defines a VME adc/tac CAEN V879
// Keywords:
//////////////////////////////////////////////////////////////////////////////

class TMrbCaen_V879 : public TMrbVMEModule {

	public:
		enum				{	kSegSize			=	0x10000	};
		enum				{	kAddrMod			=	0x39	};

		enum EMrbOffsets	{	kOffsOutput			=	0x0,
								kOffsFirmWare		=	0x1000,
								kOffsGeoAddr		=	0x1002,
								kOffsBitSet1		=	0x1006,
								kOffsBitClear1		=	0x1008,
								kOffsStatus1		=	0x100E,
								kOffsControl1		=	0x1010,
								kOffsAddrHigh		=	0x1012,
								kOffsAddrLow		=	0x1014,
								kOffsEvtTrig		=	0x1020,
								kOffsStatus2		=	0x1022,
								kOffsEvtCntLow		=	0x1024,
								kOffsEvtCntHigh 	=	0x1026,
								kOffsIncrEvt		=	0x1028,
								kOffsIncrOffs		=	0x102A,
								kOffsBitSet2		=	0x1032,
								kOffsBitClear2		=	0x1034,
								kOffsCrateSel		=	0x103C,
								kOffsTestEvtWrite	=	0x103E,
								kOffsEvtCntReset	=	0x1040,
								kOffsRangeSlope 	=	0x1060,
								kOffsRangeOffset	=	0x1062,
								kOffsThresh 		=	0x1080
							};

		enum EMrbRegisters	{	kRegFirmWare,
								kRegGeoAddr,
								kRegBitSet1,
								kRegBitClear1,
								kRegStatus1,
								kRegControl1,
								kRegAddrHigh,
								kRegAddrLow,
								kRegEvtTrig,
								kRegStatus2,
								kRegEvtCntLow,
								kRegEvtCntHigh,
								kRegIncrEvt,
								kRegIncrReg,
								kRegBitSet2,
								kRegBitClear2,
								kRegCrateSel,
								kRegTestEvtWrite,
								kRegEvtCntReset,
								kRegThresh
							};

		enum				{	kBitSet1SelAddrIntern 				=	BIT(4)	};
		enum				{	kBitControl1ProgResetModule 		=	BIT(4)	};
		enum				{	kBitSet2Offline 					=	BIT(1),
								kBitSet2OverRangeDis				=	BIT(3),
								kBitSet2LowThreshDis				=	BIT(4),
								kBitSet2SlideEna					=	BIT(7),
								kBitSet2AutoIncrEna 				=	BIT(11),
								kBitSet2EmptyProgEna				=	BIT(12),
								kBitSet2AllTrigEna					=	BIT(14)
							};
		
	public:

		TMrbCaen_V879() {};  												// default ctor
		TMrbCaen_V879(const Char_t * ModuleName, UInt_t BaseAddr, Bool_t IsTac = kFALSE); 	// define a new adc
		~TMrbCaen_V879() {};												// default dtor

		Bool_t MakeReadoutCode(ofstream & RdoStrm, TMrbConfig::EMrbModuleTag TagIndex);  	// generate part of code
		Bool_t MakeReadoutCode(ofstream & RdoStrm, TMrbConfig::EMrbModuleTag TagIndex, TMrbVMEChannel * Channel, Int_t Value = 0);  	// generate code for given channel

		virtual inline const Char_t * GetMnemonic() const { return("caen_v879"); }; 	// module mnemonic

		inline void SetFFMode(Bool_t FFFlag = kTRUE) { fFFMode = FFFlag; };
		inline Bool_t IsFFMode() const { return(fFFMode); };

		virtual Bool_t CheckSubeventType(TMrbSubevent * Subevent) const;		// check if subevent type is [10,4x]

		inline Bool_t HasRandomReadout() const { return(kFALSE); };

		inline void SetFineThresh(Bool_t FineFlag = kTRUE) { fFineThresh = FineFlag; }; // lower thresh in steps of 2 bits
		inline Bool_t HasFineThresh() const { return(fFineThresh); };

		inline void SetZeroSuppression(Bool_t ZsFlag = kTRUE) { fZeroSuppression = ZsFlag; };	// zero compression on/off
		inline Bool_t HasZeroSuppression() const { return(fZeroSuppression); };
		
		inline void SetOverRangeCheck(Bool_t OrFlag = kTRUE) { fOverRangeCheck = OrFlag; }; 	// range check on/off
		inline Bool_t HasOverRangeCheck() const { return(fOverRangeCheck); };
		
		Bool_t SetRange(Int_t Slope, Int_t Offs);					// set tac range
		inline Int_t GetRangeSlope() { return(fRangeSlope); };
		inline Int_t GetRangeOffset() { return(fRangeOffset); };


		virtual inline Bool_t HasPrivateCode() const { return(kTRUE); }; 			// use private code files
		virtual inline const Char_t * GetPrivateCodeFile() const { return("Module_Caen_Vxxx"); };
		
		inline Bool_t IsTac() { return(fIsTac); };

		inline void Help() { gSystem->Exec(Form("mrbHelp %s", this->ClassName())); };

	protected:
		void DefineRegisters(); 							// define vme registers

	protected:
		Bool_t fIsTac;
		Bool_t fFFMode;
		Bool_t fFineThresh;

		Bool_t fZeroSuppression;
		Bool_t fOverRangeCheck;

		Int_t fRangeSlope;
		Int_t fRangeOffset;

	ClassDef(TMrbCaen_V879, 1)		// [Config] CAEN V879, 32 x 4K peak sensing VME ADC/TAC
};

#endif
 TMrbCaen_V879.h:1
 TMrbCaen_V879.h:2
 TMrbCaen_V879.h:3
 TMrbCaen_V879.h:4
 TMrbCaen_V879.h:5
 TMrbCaen_V879.h:6
 TMrbCaen_V879.h:7
 TMrbCaen_V879.h:8
 TMrbCaen_V879.h:9
 TMrbCaen_V879.h:10
 TMrbCaen_V879.h:11
 TMrbCaen_V879.h:12
 TMrbCaen_V879.h:13
 TMrbCaen_V879.h:14
 TMrbCaen_V879.h:15
 TMrbCaen_V879.h:16
 TMrbCaen_V879.h:17
 TMrbCaen_V879.h:18
 TMrbCaen_V879.h:19
 TMrbCaen_V879.h:20
 TMrbCaen_V879.h:21
 TMrbCaen_V879.h:22
 TMrbCaen_V879.h:23
 TMrbCaen_V879.h:24
 TMrbCaen_V879.h:25
 TMrbCaen_V879.h:26
 TMrbCaen_V879.h:27
 TMrbCaen_V879.h:28
 TMrbCaen_V879.h:29
 TMrbCaen_V879.h:30
 TMrbCaen_V879.h:31
 TMrbCaen_V879.h:32
 TMrbCaen_V879.h:33
 TMrbCaen_V879.h:34
 TMrbCaen_V879.h:35
 TMrbCaen_V879.h:36
 TMrbCaen_V879.h:37
 TMrbCaen_V879.h:38
 TMrbCaen_V879.h:39
 TMrbCaen_V879.h:40
 TMrbCaen_V879.h:41
 TMrbCaen_V879.h:42
 TMrbCaen_V879.h:43
 TMrbCaen_V879.h:44
 TMrbCaen_V879.h:45
 TMrbCaen_V879.h:46
 TMrbCaen_V879.h:47
 TMrbCaen_V879.h:48
 TMrbCaen_V879.h:49
 TMrbCaen_V879.h:50
 TMrbCaen_V879.h:51
 TMrbCaen_V879.h:52
 TMrbCaen_V879.h:53
 TMrbCaen_V879.h:54
 TMrbCaen_V879.h:55
 TMrbCaen_V879.h:56
 TMrbCaen_V879.h:57
 TMrbCaen_V879.h:58
 TMrbCaen_V879.h:59
 TMrbCaen_V879.h:60
 TMrbCaen_V879.h:61
 TMrbCaen_V879.h:62
 TMrbCaen_V879.h:63
 TMrbCaen_V879.h:64
 TMrbCaen_V879.h:65
 TMrbCaen_V879.h:66
 TMrbCaen_V879.h:67
 TMrbCaen_V879.h:68
 TMrbCaen_V879.h:69
 TMrbCaen_V879.h:70
 TMrbCaen_V879.h:71
 TMrbCaen_V879.h:72
 TMrbCaen_V879.h:73
 TMrbCaen_V879.h:74
 TMrbCaen_V879.h:75
 TMrbCaen_V879.h:76
 TMrbCaen_V879.h:77
 TMrbCaen_V879.h:78
 TMrbCaen_V879.h:79
 TMrbCaen_V879.h:80
 TMrbCaen_V879.h:81
 TMrbCaen_V879.h:82
 TMrbCaen_V879.h:83
 TMrbCaen_V879.h:84
 TMrbCaen_V879.h:85
 TMrbCaen_V879.h:86
 TMrbCaen_V879.h:87
 TMrbCaen_V879.h:88
 TMrbCaen_V879.h:89
 TMrbCaen_V879.h:90
 TMrbCaen_V879.h:91
 TMrbCaen_V879.h:92
 TMrbCaen_V879.h:93
 TMrbCaen_V879.h:94
 TMrbCaen_V879.h:95
 TMrbCaen_V879.h:96
 TMrbCaen_V879.h:97
 TMrbCaen_V879.h:98
 TMrbCaen_V879.h:99
 TMrbCaen_V879.h:100
 TMrbCaen_V879.h:101
 TMrbCaen_V879.h:102
 TMrbCaen_V879.h:103
 TMrbCaen_V879.h:104
 TMrbCaen_V879.h:105
 TMrbCaen_V879.h:106
 TMrbCaen_V879.h:107
 TMrbCaen_V879.h:108
 TMrbCaen_V879.h:109
 TMrbCaen_V879.h:110
 TMrbCaen_V879.h:111
 TMrbCaen_V879.h:112
 TMrbCaen_V879.h:113
 TMrbCaen_V879.h:114
 TMrbCaen_V879.h:115
 TMrbCaen_V879.h:116
 TMrbCaen_V879.h:117
 TMrbCaen_V879.h:118
 TMrbCaen_V879.h:119
 TMrbCaen_V879.h:120
 TMrbCaen_V879.h:121
 TMrbCaen_V879.h:122
 TMrbCaen_V879.h:123
 TMrbCaen_V879.h:124
 TMrbCaen_V879.h:125
 TMrbCaen_V879.h:126
 TMrbCaen_V879.h:127
 TMrbCaen_V879.h:128
 TMrbCaen_V879.h:129
 TMrbCaen_V879.h:130
 TMrbCaen_V879.h:131
 TMrbCaen_V879.h:132
 TMrbCaen_V879.h:133
 TMrbCaen_V879.h:134
 TMrbCaen_V879.h:135
 TMrbCaen_V879.h:136
 TMrbCaen_V879.h:137
 TMrbCaen_V879.h:138
 TMrbCaen_V879.h:139
 TMrbCaen_V879.h:140
 TMrbCaen_V879.h:141
 TMrbCaen_V879.h:142
 TMrbCaen_V879.h:143
 TMrbCaen_V879.h:144
 TMrbCaen_V879.h:145
 TMrbCaen_V879.h:146
 TMrbCaen_V879.h:147
 TMrbCaen_V879.h:148
 TMrbCaen_V879.h:149
 TMrbCaen_V879.h:150
 TMrbCaen_V879.h:151
 TMrbCaen_V879.h:152
 TMrbCaen_V879.h:153
 TMrbCaen_V879.h:154
 TMrbCaen_V879.h:155
 TMrbCaen_V879.h:156
 TMrbCaen_V879.h:157
 TMrbCaen_V879.h:158
 TMrbCaen_V879.h:159
 TMrbCaen_V879.h:160
 TMrbCaen_V879.h:161