#ifndef __TMrbDGFData_h__
#define __TMrbDGFData_h__
#include "TObject.h"
#include "TSystem.h"
#include "TString.h"
#include "TArrayS.h"
#include "TMrbNamedX.h"
#include "TMrbLofNamedX.h"
class TMrbDGFData : public TObject {
friend class TMrbDGF;
public:
enum { kFPGAMaxSize = 0x10000 };
enum { kDSPMaxSize = 0x8000 };
enum EMrbDGFFileType { kFileUndef = 1,
kFileAscii = 2,
kFileBinary = 3
};
enum EMrbFPGAType { kSystemFPGA,
kFippiFPGA
};
enum { kNofDSPInputParams = 256 };
enum { kNofDSPOutputParams = 160 };
enum { kNofDSPInparModule = 64 };
enum { kNofDSPInparChannel = 48 };
enum { kDSPInparStartAddr = 0x4000 };
enum { kDSPOutparStartAddr = kDSPInparStartAddr + kNofDSPInputParams };
enum EMrbCamacCSR {
kRunEna = BIT(0),
kNewRun = BIT(1),
kEnaLAM = BIT(3),
kDSPReset = BIT(4),
kDSPError = BIT(12),
kActive = BIT(13),
kLAMActive = BIT(14)
};
enum { kCamacCSRMask = kRunEna | kNewRun | kEnaLAM |
kDSPError | kActive | kLAMActive
};
enum EMrbCamacICSR {
kSystemFPGAReset = BIT(0),
kFippiFPGA0Reset = BIT(4),
kFippiFPGA1Reset = BIT(5),
kFippiFPGA2Reset = BIT(6),
kFippiFPGA3Reset = BIT(7),
kConnectDSPFromRight = BIT(8),
kConnectDSPFromLeft = BIT(9),
kTerminateDSP = BIT(10),
kConnectFastFromRight = BIT(11),
kConnectFastFromLeft = BIT(12),
kTerminateFast = BIT(13),
kSwitchBusNormal = 0
};
enum { kFippiFPGAReset = kFippiFPGA0Reset | kFippiFPGA1Reset |
kFippiFPGA2Reset | kFippiFPGA3Reset
};
enum { kFPGAReset = kSystemFPGAReset | kFippiFPGAReset };
enum { kConnectDSPTrigger = kConnectDSPFromRight | kConnectDSPFromLeft |
kTerminateDSP
};
enum { kConnectFastTrigger = kConnectFastFromRight | kConnectFastFromLeft |
kTerminateFast
};
enum { kSwitchBus = kConnectDSPTrigger | kConnectFastTrigger };
enum { kCamacICSRMask = kFPGAReset | kSwitchBus };
enum EMrbModCSRA {};
enum EMrbModCSRB { kCallUserCode = 1 };
enum EMrbRunTask {
kRunSlowControl = 0,
kRunStdListMode = 0x100,
kRunStdListModeNoTrace = 0x101,
kRunStdListModeShort4 = 0x102,
kRunStdListModeShort2 = 0x103,
kRunFastListMode = 0x200,
kRunFastListModeNoTrace = 0x201,
kRunFastListModeShort4 = 0x202,
kRunFastListModeShort2 = 0x203,
kRunMCA = 0x301
};
enum EMrbControlTask {
kProgramDACs = 0,
kConnectInputs = 1,
kDisconnectInputs = 2,
kCalibrate = 3,
kSampleADCs = 4,
kUpdateFPGA = 5,
kReadHistoFirstPage = 9,
kReadHistoNextPage = 10
};
enum EMrbChanCSRA {
kGroupTriggerOnly = BIT(0),
kIndivLiveTime = BIT(1),
kGoodChannel = BIT(2),
kReadAlways = BIT(3),
kEnableTrigger = BIT(4),
kTriggerPositive = BIT(5),
kGFLTValidate = BIT(6),
kHistoEnergies = BIT(7),
kHistoBaselines = BIT(8),
kCorrBallDeficit = BIT(9),
kComputeCFT = BIT(10),
kEnaMultiplicity = BIT(11),
kBipolarSignals = BIT(15)
};
enum EMrbUserPsaData { kPsaBaseline03 = 0,
kPsaCutOff01,
kPsaCutOff23,
kPsaT0Thresh01,
kPsaT0Thresh23,
kPsaT90Thresh03,
kPsaPSACh0,
kPsaPSACh1,
kPsaPSACh2,
kPsaPSACh3,
kPsaPSALength01,
kPsaPSALength23,
kPsaPSAOffset01,
kPsaPSAOffset23,
kPsaTFACutOff01,
kPsaTFACutOff23
};
enum EMrbUserPsaCSR {
kT0 = BIT(0),
kT90 = BIT(1),
kTslope = BIT(2),
kQmax = BIT(3),
kUseEnergyCutTFA = BIT(4),
kUseTFA = BIT(5),
kInitTFA = BIT(6),
kForceAveTiming = BIT(7),
kAvePulseShape = BIT(8),
kAveRefT0 = BIT(9),
kAveRefT90 = BIT(10),
kRefPsaOffsLength = BIT(11),
kQuadInterpolT0 = BIT(12),
kInterpolT0Tslope = BIT(13),
kOverwriteGSLT = BIT(14),
kInterpolT50T90 = BIT(15)
};
enum { kChanCSRAMask = 0xffff };
enum EMrbChanCSRB {};
enum EMrbDGFStatusDBits {
kSystemFPGACodeRead = BIT(2),
kFippiFPGARevDCodeRead = BIT(3),
kFippiFPGARevECodeRead = BIT(4),
kDSPCodeRead = BIT(5),
kParamNamesRead = BIT(6)
};
enum { kNofChannels = 4 };
enum { kNofMCAPages = 8 };
enum { kMCAPageSize = 32 * 1024 };
enum { kUntrigTraceLength = 8192 };
enum { kChannelPattern = 0xF };
enum EMrbDGFRevision { kRevUnknown = -1,
kOrigRevD = 3,
kOrigRevE = 4,
kRevD = 0,
kRevE = 1
};
enum { kNofRevs = kRevE - kRevD + 1 };
public:
TMrbDGFData();
~TMrbDGFData() { Reset(); };
Int_t ReadFPGACodeBinary(EMrbFPGAType FPGAType, const Char_t * CodeFile = "", Int_t Rev = kRevUnknown, Bool_t Forced = kFALSE);
Int_t ReadFPGACodeBinary(const Char_t * FPGAType, const Char_t * CodeFile = "", Int_t Rev = kRevUnknown, Bool_t Forced = kFALSE);
Int_t ReadFPGACodeAscii(EMrbFPGAType FPGAType, const Char_t * CodeFile = "", Int_t Rev = kRevUnknown, Bool_t Forced = kFALSE);
Int_t ReadFPGACodeAscii(const Char_t * FPGAType, const Char_t * CodeFile = "", Int_t Rev = kRevUnknown, Bool_t Forced = kFALSE);
Int_t ReadFPGACode(EMrbFPGAType FPGAType, const Char_t * CodeFile = "", Int_t Rev = kRevUnknown, Bool_t Forced = kFALSE);
Int_t ReadFPGACode(const Char_t * FPGAType, const Char_t * CodeFile = "", Int_t Rev = kRevUnknown, Bool_t Forced = kFALSE);
Bool_t FPGACodeRead(EMrbFPGAType FPGAType, Int_t Rev = kRevUnknown) const;
Bool_t FPGACodeRead(const Char_t * FPGAType, Int_t Rev = kRevUnknown) const;
inline Int_t GetFPGACodeSize(EMrbFPGAType FPGAType, Int_t Rev = kRevUnknown) const {
return (FPGAType == kSystemFPGA ? fSystemFPGASize : fFippiFPGASize[Rev]);
};
inline UShort_t * GetFPGACodeAddr(EMrbFPGAType FPGAType, Int_t Rev = kRevUnknown) {
return (FPGAType == kSystemFPGA ? (UShort_t *) fSystemFPGACode.GetArray() : (UShort_t *) fFippiFPGACode[Rev].GetArray());
};
Int_t ReadDSPCodeBinary(const Char_t * CodeFile = "", Bool_t Forced = kFALSE);
Int_t ReadDSPCodeAscii(const Char_t * CodeFile = "", Bool_t Forced = kFALSE);
Int_t ReadDSPCode(const Char_t * CodeFile = "", Bool_t Forced = kFALSE);
inline Bool_t DSPCodeRead() const { return((fStatusD & kDSPCodeRead) != 0); };
inline Int_t GetDSPCodeSize() const { return(fDSPSize); };
UShort_t * GetDSPCodeAddr() { return((UShort_t *) fDSPCode.GetArray()); };
Int_t ReadNameTable(const Char_t * ParamFile = "", Bool_t Forced = kFALSE);
Int_t AddToNameTable(const Char_t * ParamFile, const Char_t * Comment = NULL);
Int_t AddToNameTable(const Char_t * ParamName, Int_t Index, const Char_t * Comment = NULL);
inline TMrbNamedX * FindParam(const Char_t * ParamName) const { return((TMrbNamedX *) fParamNames.FindByName(ParamName)); };
inline TMrbNamedX * FindParam(Int_t Offset) const { return((TMrbNamedX *) fParamNames.FindByIndex(Offset)); };
TMrbNamedX * FindParam(Int_t Channel, const Char_t * ParamName);
inline TMrbNamedX * FirstParam() const { return((TMrbNamedX *) fParamNames.First()); };
inline TMrbNamedX * NextParam(TMrbNamedX * Param) const { return((TMrbNamedX *) fParamNames.After(Param)); };
inline Bool_t ParamNamesRead() const { return((fStatusD & kParamNamesRead) != 0); };
inline Int_t GetNofParams() const { return(fNofParams); };
inline TMrbLofNamedX * GetLofParamNames() { return(&fParamNames); };
inline Int_t GetXiaRelease() const { return(fXiaRelease); };
void PrintXiaRelease() const;
void Print(Option_t * Option) const { TObject::Print(Option); };
void Print() const;
inline void SetLocal(Bool_t LocalFlag) { fLocalData = LocalFlag; };
inline void SetVerboseMode(Bool_t VerboseFlag = kTRUE) { fVerboseMode = VerboseFlag;};
inline Bool_t IsVerbose() const { return(fVerboseMode); };
inline void Help() { gSystem->Exec(Form("mrbHelp %s", this->ClassName())); };
public:
TMrbLofNamedX fLofDGFStatusDBits;
TMrbLofNamedX fLofDGFFileTypes;
TMrbLofNamedX fLofFPGATypes;
TMrbLofNamedX fLofCamacCSRBits;
TMrbLofNamedX fLofCamacICSRBits;
TMrbLofNamedX fLofModCSRABits;
TMrbLofNamedX fLofModCSRBBits;
TMrbLofNamedX fLofChanCSRABits;
TMrbLofNamedX fLofUserPsaCSRBits;
TMrbLofNamedX fLofRunTasks;
TMrbLofNamedX fLofControlTasks;
protected:
void Reset();
void Setup();
Bool_t CheckXiaRelease();
protected:
Bool_t fVerboseMode;
UInt_t fXiaRelease;
UInt_t fStatusD;
Bool_t fLocalData;
TString fDSPFile;
EMrbDGFFileType fDSPType;
Int_t fDSPSize;
TArrayS fDSPCode;
TString fSystemFPGAFile;
EMrbDGFFileType fSystemFPGAType;
Int_t fSystemFPGASize;
TArrayS fSystemFPGACode;
TString fFippiFPGAFile[kNofRevs];
EMrbDGFFileType fFippiFPGAType[kNofRevs];
Int_t fFippiFPGASize[kNofRevs];
TArrayS fFippiFPGACode[kNofRevs];
TString fParamFile;
Int_t fNofParams;
TMrbLofNamedX fParamNames;
ClassDef(TMrbDGFData, 1)
};
#endif